1. Field of the Invention
The present invention relates to an image signal processing device by which an image signal corresponding to one frame is divided into a plurality of parts to be recorded on a plurality of tracks of a recording medium, such as a magnetic disk.
2. Description of the Related Art
In a typical still video device, an image signal inputted thereto is frequency-modulated and recorded on a magnetic disk, and the frequency band of the signal recorded on the magnetic disk is regulated. Nevertheless, the bandwidth of the signal is limited, due to the construction of the disk device, and thus, cannot be freely expanded. Accordingly, in a conventional still video device, when an image signal having a high quality or broad bandwidth is inputted to the still video device, a limit is imposed on the resolution of the image and thus, the quality of the image is limited.
The inventor proposed, in U.S. patent application Ser. No. 07/913,191, corresponding to Japanese Unexamined Patent Publication Nos. 5-30461, 5-48999, 5-56391 and 5-56392), a still video device in which an image signal corresponding to one frame is divided into a plurality of parts and stored in a memory, and the divided parts of the image signal are time-expanded and recorded on a plurality of tracks of a recording medium, such as a magnetic disk, so that a high quality image can be obtained without changing the bandwidth of a signal recorded in the recording medium.
In this still video device, when the image signal is A/D converted to be stored in the memory, the standard of the A/D conversion is set by using a pedestal level provided at a starting point of each of horizontal scanning lines. Namely, in a clamping circuit, the pedestal level is clamped based on a clamp pulse such as a burst flag signal generated in accordance with a horizontal synchronizing signal, and shifted to the standard level of the A/D conversion.
As shown in FIG. 1, however, in the vertical synchronizing period Vsync, since there is no pedestal level (i.e., clamp pulse), the clamping circuit must be stopped. Accordingly, in the vertical synchronizing period Vsync, the output voltage of the clamping circuit is lowered due to the time constant of the clamping circuit, and it takes some time until the output voltage recovers to the normal value after a new horizontal synchronizing signal is inputted to the clamp circuit.
Namely, regarding a horizontal scanning line N which is provided immediately after the vertical synchronizing period Vsync, the A/D conversion value is set to a lower value than the normal value as indicated by the reference M. Therefore, as shown in FIG. 2, in the upper portion of each of the divided frames, the luminance signal level is made low, and thus, the portion immediately after the join portion J formed by combining the two divided frames is darkened.